FIG. 1 is a cross section of a semiconductor element including a semiconductor device having a conventional row pad structure. As illustrated in FIG. 1, the semiconductor element 100 includes the semiconductor device 110 and a printed circuit board (PCB) 130, for example, having a ball grid array (BGA) package type.
The semiconductor device 110 may be a bare semiconductor chip, for example, a dynamic random access memory (DRAM), and includes a pad layer 111 on a surface adjacent the PCB 130. A row pad, which is included in the pad layer 111, is electrically coupled to a plurality of solder balls 131 on a surface of the PCB 130 opposite the pad layer 111 via a corresponding metal line ML. The solder balls 131 may also be electrically coupled to an external device (not shown).
Referring now to FIG. 2, a plan view of a semiconductor element including a semiconductor device having a single row pad structure will be discussed. As illustrated in FIG. 2, a conventional semiconductor element 200 may include a semiconductor device 210 and a PCB 230. A plurality of pads composing a single row pad structure in the pad layer of the semiconductor device 210 are provided in the center of the semiconductor device 210. Such a pad arrangement may be referred to as a center pad arrangement. The pads include first through eighth signal pads SP1 through SP8 and first through seventh power pads PP1 through PP7. Control signals, such as input/output data signals and command signals, may be transmitted via the first through eighth signal pads SP1 through SP8. A power supply voltage, a ground voltage, or a termination voltage is applied to the first through seventh power pads PP1 through PP7.
For example, the first and second signal pads SP1 and SP2 provided between a first input buffer INRCV1 and a first output buffer OUTDRV1 may be data input/output (DQ) pads. A DQ input/output (IO) block may include the first input buffer INRCV1, the first output buffer OUTDRV1, and the DQ pads (first and second signal pads SP1 and SP2) provided in a single unit. The DQIO block may be repeatedly provided in a single row pad structure. The power pads may be provided between each of the DQIO blocks.
The semiconductor device 210, which may be a bare semiconductor chip, may include circuits such as first through fourth input buffers INRCV1 through INRCV 4 and first through fourth output buffers OUTDRV1 through OUTDRV 4. The input buffers may: be referred to as input receivers and the output buffers may be referred to as output drivers.
The first through eighth signal pads SP1 through SP8 and the first through seventh power pads PP1 through PP7 may be respectively bonded to first ends of first through fifteenth connection lines CL1 through CL15, which form metal patterns. The second ends of the first through fifteenth connection lines CL1 through CL15 may be bonded to solder balls 231 of the PCB 230. Each of the first through fifteenth connection lines CL1 through CL15 may extend from the center of the semiconductor device 210 to an edge of the PCB 230.
As the size of semiconductor devices continue to decrease, it may become increasingly difficult to arrange the signal and power pads in a single row pad structure. Thus, some conventional semiconductor devices include two-row pad structures as illustrated in FIG. 3. FIG. 3 is a plan view of a conventional semiconductor element including a semiconductor device having a two-row pad structure. As illustrated therein, a conventional semiconductor element 300 includes a semiconductor device 310 and a PCB 330.
A plurality of pads forming a two-row pad structure in the pad layer of the semiconductor device 310 are provided in a center pad arrangement. The pads include first through ninth signal pads SP1 through SP9 and first through ninth power pads PP1 through PP9. Control signals, such as input/output data signals and command signals, may be transmitted via the first through ninth signal pads SP1 through SP9. A power supply voltage, a ground voltage, or a termination voltage may be applied to the first through ninth power pads PP1 through PP9.
For example, the first and second signal pads SP1 and SP2 (DQ pads) may be provided between a first input buffer INRCV1 and a first output buffer OUTDRV1 and may be data input/output pads (DQIO). The first and second signal pads SP1 and SP2, the first input buffer INRCV1 and the first output buffer OUTDRV1 may form a DQIO block. The DQIO block may be repeatedly provided in the two-row pad structure of FIG. 3.
The DQ pads of the DQIO block may be provided in a first row of pads or in a second row of pads of a two-row pad structure. When the DQ pads are provided in the first row of pads, power pads may be provided the second row of pads. When the DQ pads are provided in the second row of pads, power pads may be provided in the first row of pads. Providing two-rows of pads as illustrated in FIG. 3 may allow the chip size of a semiconductor device to be decreased.
The semiconductor device 310 of FIG. 2, which may be a bare semiconductor chip, may include circuits such as first through fourth input buffers INRCV1 through INRCV 4 and first through fourth output buffers OUTDRV1 through OUTDRV4. A clock signal may be transmitted to the first through fourth input buffers INRCV1 through INRCV4 and the first through fourth output buffers OUTDRV1 through OUTDRV4 via a signal line SL. The clock signal may be a control signal input through the ninth signal pad SP9. As illustrated in FIG. 4, the first through fourth input buffers INRCV1 through INRCV4 may be located between a first row of pads and a second row of pads and the first through fourth output buffers OUTDRV1 through OUTDRV4 may be located between the edges of the semiconductor device 410 and a first row of pads and a second row of pads, respectively.
The first through ninth signal pads SP1 through SP9 and the first through ninth power pads PP1 through PP9 may be respectively bonded to first ends of the first through eighteenth connection lines CL1 through CL18, which form metal patterns. The second ends of the the first through eighteenth connection lines CL1 through CL18 may be respectively bonded to solder balls 331 of the PCB 330. Each of the first through eighteenth connection lines CL1 through CL18 may extend from one of the first through ninth single pads SP1 through SP9 and the first through ninth power pads PP1 through PP9 to an edge of the PCB 330. Thus, the semiconductor device 310 may be electrically coupled to an external device (not shown).
However, although the two-row pad structure of FIGS. 3 and 4 provides improvements over the single row pad structure, as the size of semiconductor devices continue to decrease, it may still be difficult to arrange all of the pads in a two-row pad structure. Furthermore, as the length of a signal line SL, which is configured to distribute a clock signal input through the ninth signal pad SP9, increases, the quality of a clock signal may be reduced due to resistive/capacitive (RC) delay.